BENDIX BENDIX 7129 Manual de usuario descargar pdf (Pagina 3)

ADV7129

–3–

REV. 0

TIMING SPECIFICATIONS

Parameter Conditions Min Typ Max Units

CLOCK CONTROL & PIXEL PORT

LOADIN Clocking Rate, f

LCLK

10 45 MHz

LOADIN Cycle Time, t

16.67 ns

LOADIN Low Time, t

6.67 ns

LOADIN High Time, t

6.67 ns

LOADIN to LOADOUT Delay, t

5ns

Pixel Setup Time, t

10 ns

Pixel Hold Time, t

42 ns

MPU PORT

W, C0, C1 Setup Time, t

10 2.5 ns

W, C0, C1 Hold Time, t

10 0.5 ns

CE Low Time, t

25 ns

CE High Time, t

25 ns

CE Asserted to Data-Bus Driven, t

25 ns

CE Asserted to Data-Bus Valid, t

20 ns

CE Negated to Data-Bus Invalid, t

1ns

CE Negated to Data-Bus Three Stated, t

15 ns

Write Data (D7–D0) Setup Time, t

10 ns

Write Data (D7–D0) Hold Time, t

10 ns

ANALOG OUTPUTS

Analog Output Delay, t

@ 360 MHz 5 ns

Analog Output Rise/Fall Time, t

0.8 ns

Analog Output Transition Time, t

25 ns

RGB Analog Output Skew, t

1.5 ns

Pipeline Delay, t

19 PCLKs

PLL PERFORMANCE

Jitter (1σ) (LOADIN = 45 MHz) 55 ps rms

NOTES

TTL inputs values are 0 V to 3 V with input rise/fall times ≥3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-

puts. Analog output load ≤10 pF. Databus (D7–D0) loaded as shown in Figure 1. Digital output load for SENSE ≤30 pF.

±5% for all versions.

Temperature range (T

MIN

to T

MAX

), 0°C to +70°C.

Pixel Port consists of the following inputs: Pixel Inputs: RED [A-H], BLUE [A-H], GREEN [A-H].

Output Delay is measured from the 50% rising edge of LOADIN to the 50% point of full-scale transition on the A pixel. t

includes the analog delay due to DACs

and internal gate transitions plus the pipeline stages delay. The output delay for pixels B-H will be the output delay to the A pixel (t

) plus the appropriate number

of clock cycles. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Settling time is measured from the 50% point of full-scale

transition to the output remaining within 1%. (Settling Time does not include clock and data feedthrough.)

Jitter is measured by triggering on the output clock, delayed by 15 µs and then measuring the time period from the trigger edge to the next edge of the output clock

after the delay. This measurement is repeated multiple times and the rms value is determined.

Specifications subject to change without notice.

= +5 V, V

REF

= +1.235 V, R

RSET

, R

GSET,

BSET

= 280 V, R

= 25 V for IOG, IOR, IOB, C

= 10 pF.

All specifications T

MIN

to T

MAX

unless otherwise noted.)

TO OUTPUT PIN +2.1V

100pF

SINK

SOURCE

Figure 1. LOADIN vs. Pixel Input Data

1 2 3 4 5 6 7 8 ... 19 20

Comentarios a estos manuales

Sin comentarios

BENDIX BENDIX 7129 Manual de usuario Pagina 3

Comentarios a estos manuales

Relacionado con productos y manuales para Lavadoras BENDIX BENDIX 7129