BENDIX BENDIX 7129 Manual de usuario descargar pdf (Pagina 9)

ADV7129

–9–

REV. 0

Mnemonic Function

IOR, IOG, IOB Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are

specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50 Ω or 75 Ω loads.

IOR, IOG, IOB Differential Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video

outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 50 Ω or

75 Ω loads. If the complementary outputs are not required, then these outputs should be tied to GND.

COMP

Red Compensation pin. This pin should be bypassed to V

with 0.01 µF capacitor.

COMP

Green Compensation pin. This pin should be bypassed to V

with 0.01 µF capacitor.

COMP

Blue Compensation pin. This pin should be bypassed to V

with 0.01 µF capacitor.

RSET,

GSET,

BSET

DAC Output Full-Scale Adjust Control (Analog Input): A resistor from this pin to ground sets the current

in the DACs. The current in the DACs is set according to the equations:

OUT

= 12,950 × V

REF

SET

(SYNC not encoded on the DAC Output)

OUT

= 18,137 × V

REF

SET

(SYNC encoded on the DAC Output)

To generate RS 343-A video levels on the DAC outputs, a resistor value of 280 Ω is recommended for

doubly terminated 50 Ω lines. Any combination of R

SET

value, DAC termination resistor and programming

SYNC and pedestal are possible provided that the maximum DAC current and the DAC output compli-

ance specifications are adhered to.

For example, in a doubly terminated 50 Ω system with no

SYNC or pedestal encoded on the DAC outputs,

an R

SET

value of 280 Ω gives a DAC full-scale output of 52.8 mA, i.e., a white-to-black value of 1.4 V.

This example would give a 6 dB reduction in noise and feedthrough on the DAC outputs (compared to a

0.7 V full-scale value), but may require a 0.5X splitter at the monitor.

BIAS

Red Bias node. This node should be decoupled to V

with a 0.01 µF capacitor.

BIAS

Green Bias node. This node should be decoupled to V

with a 0.01 µF capacitor.

BIAS

Blue Bias node. This node should be decoupled to V

with a 0.01 µF capacitor.

SENSE/

SYNCOUT Comparator Sense Output (TTL Compatible Output). This output will be logic “1” if one or more of the

analog outputs exceeds the internal voltage of the SENSE comparator circuit. It can be used to determine

the absence of a CRT monitor. The value of the SENSE Output corresponds to the current pixel at the out-

puts. The output can drive one CMOS load. This pin can alternately be programmed to be a TTL sync

output which is a delayed version of

CSYNC.

REF

Voltage Reference (Analog Input/Output): This should always have a 0.1 µF decoupling capacitor attached

between V

REF

and V

. If nothing else is connected then the DACs are driven by the internal voltage refer-

ence. If it is required to use a more accurate reference, then this pin acts as an overdrive input. An external

1.235 V voltage reference such as the AD1580 or equivalent is recommended to drive this input. (Note: It is

not recommended to use a resistor network to generate the voltage reference.)

Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be connected together

to one common +5 V filtered analog power supply.

GND Analog Ground. The part contains multiple ground pins, all should be connected together to the system’s

ground plane.

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